1. Field of the Invention
The present invention relates in general to integrated circuits, and more particularly to memory arrays in integrated circuits. Still more particularly, the present invention relates to a method for stress testing decoders and periphery circuits used with memory arrays.
2. Description of the Prior Art
Memory arrays use many different circuits in order to operate. For example, row decoders, column decoders, write decoders, pre-coding and post-coding circuits may be used. Stress testing of memory arrays, decoders and other periphery circuits used with memory arrays is typically accomplished by applying a stress voltage to the integrated circuit. Most latent defects within the memory array and various circuits are detected as a result of stress testing.
Stress testing of decoders and other periphery circuits used with memory arrays, however, is typically not performed due to the length of time required for testing. In order to stress test each gate in the decoders and other periphery circuits, each and every address combination must be selected individually. A stress voltage would then be applied to the integrated circuit. However, those skilled in the art will appreciate that selecting and stressing each and every address combination requires quite a bit of time. Consequently, stress testing of decoders and other periphery circuits is usually not performed.
For example, to test the decoders and other circuits used with a 128K by 8k memory array, 128,000 address combinations must be activated individually, and then set to a stress voltage. Understandably, cycling through 128,000 address combinations would be a very time consuming task. A result of not performing a stress test is that latent defects in the decoders and periphery circuitry go undetected. This results in the production of marginal memory arrays.
Therefore, it would be desirable to provide a method for stress testing decoders and other periphery circuits used with a memory array. It is also desirable that such a method not increase the complexity of the testing or fabrication of an integrated circuit.